For high speed data transfer, a serializer/deserializer (SERDES) circuit is often used as an interface between an exterior of a chip and an interior of the chip. For instance, the SERDES circuit may convert parallel data to serial data for transmission over air waves or along a wire, for example, and to convert serial data to parallel data for processing by the chip. A SERDES transmitter includes circuitry for serializing parallel data, and a SERDES receiver includes circuitry for deserializing serial data.
Receivers used in high speed SERDES are typically implemented in current mode logic (CML) circuitry. The implementation of receiver components such as slicers and phase interpolators using CML technology often provides relatively high performance (e.g., jitter tolerance, power supply sensitivity, input amplitude sensitivity) as compared to other technologies. However, implementation of such components in CML technology results in relatively high power consumption and loss of chip area due to the size of the components in the SERDES circuit when implemented using CML technology. Incorporation of additional functionalities, such as eye monitoring, increases power consumption and chip area usage. Eye monitors monitor a data eye of a received bit stream. Conventional SERDES receivers that have eye monitoring functionality typically include two eye monitors. One eye monitor monitors output of a data slicer and the other eye monitor monitors output of a data bar slicer. The data slicer and the data bar slicer are commonly implemented as strong arm slicers and CML slicers. Digital components such as complementary metal oxide semiconductor (CMOS) components utilize digital switches which typically consume less power and less chip area as compared to their analog counterparts. However, such digital components often are slower than their analog counterparts.